This invention relates to an image data quantizing circuit; and more particularly, to an image data quantizing circuit for quantizing a differential pixel block between a current pixel block and a predicted pixel block.
With recent enhanced requirements for high speed image signal processing, it is desirable to realize an image processing coder/decoder (codec) with a digital signal processor. In an image processor, n.times.n (n=4, 8, 16, . . . ) pixel blocks are transmitted to a transmission line. Before transmission the pixels are band compressed by a differential quantizing process. In a receiver, a recovered image can be obtained by conducting addition with a predicted image block through an inverse quantizing process.
In an effort to realize a high speed image data processor, a 2-port RAM, which has two address input ports and two data output ports, is employed as an image data processor RAM. By employing such a 2-port RAM, read and write processes can be carried out at the same time. Thus, memory access time to the image data processor RAM decreases. When memory access time decreases, the total processing speed of an image data processor can be improved.
In conventional image data processors, however, 2-port RAM circuit structures cannot satisfactorily process the huge amount of image data that must be processed.